"Distinguished Lecture: 3D MIM Capacitor Embedded in TSV: Concept, Device Demonstration, Reliability and Applications" co-organized by IET Malaysia Ne
In this work, a novel integrated capacitor, called “3D MIM Capacitor Embedded in TSV” is proposed, designed, fabricated, and characterized for application in integrated circuits (ICs) with through-silicon vias (TSVs). A significant capacitance density enhancement can be achieved for this 3D embedded capacitor, because it leverages on the high aspect ratio structure of TSVs. Compared to conventional trench capacitor, this technology does not consume additional silicon area because it is embedded in the trenches of existing TSVs, instead of dedicated trenches. An ultrahigh capacitance density of 5,621.8 nF/mm2 was envisioned according to our model, which is ~13× of 440.0 nF/mm2 from a conventional trench capacitor with the same design parameters. A leakage current density as low as 1.61×10-7 A/cm2 at 4.3V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3,776.6 nF/mm2. In addition, the reliability of the 3D MIM and potential new applications it enables are discussed.
Chuan Seng Tan, PhD
Nanyang Technological University, Singapore
For details, please visit: www.ieee.org/go/penang
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